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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05441 rev. *f revised august 01, 2007 cy62147ev18 mobl2? 4-mbit (256k x 16) static ram features very high speed: 55 ns wide voltage range: 1.65v?2.25v pin compatible with cy62147dv18 ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ultra low active power ? typical active current: 2 ma @ f = 1 mhz ultra low standby power easy memory expansion with ce and oe features automatic power down when deselected cmos for optimum speed and power available in a pb-free 48-ball vfbga package functional description the cy62147ev18 is a high performance cmos static ram organized as 256k words by 16 bits. this device features advanced circuit design to provid e ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature t hat significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: deselected (ce high) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) when a write operation is active (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. for best practice recommendati ons, refer to the cypress application note an1064, sram system guidelines . logic block diagram 256k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 bhe ble ce power down circuit
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 2 of 12 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max cy62147ev18ll 1.65 1.8 2.25 55 2 2.5 15 20 1 7 pin configuration figure 1. 48-ball vfbga pinout [2, 3] top view we a 11 a 10 a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe a 7 io 0 bhe nc a 2 a 1 ble io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss a 17 notes 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c. 2. nc pins are not connected on the die. 3. pins h1, g2, and h6 in the vfbga package are address expansion pins for 8 mb, 16 mb and 32 mb, respectively.
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 3 of 12 maximum ratings exceeding the maximum ratings may shorten the battery life of the device. user guidelines are not tested. storage temperature ................................ ?65c to + 150c ambient temperature with power applied .......................................... ?55c to + 125c supply voltage to ground potential ........................... ?0.2v to + 2.45v (v ccmax + 0.2v) dc voltage applied to outputs in high z state [4, 5] ............... ?0.2v to 2.45v (v ccmax + 0.2v) dc input voltage [4, 5] ........... ?0.2v to 2.45v (v ccmax + 0.2v) output current into outputs (low) ............................ 20 ma static discharge voltage ......................................... > 2001v (mil-std-883, method 3015) latch up current .... .............. .............. .............. ...... > 200 ma operating range device range ambient temperature v cc [6] cy62147ev18ll industrial ?40c to +85c 1.65v to 2.25v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [1] max v oh output high voltage i oh = ?0.1 ma 1.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v ih input high voltage v cc =1.65v to 2.25v 1.4 v cc + 0.2 v v il input low voltage v cc =1.65v to 2.25v ?0.2 0.4 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc(max) =2.25v i out = 0 ma cmos levels 15 20 ma f = 1 mhz v cc(max) =2.25v 2 2.5 ma i sb1 automatic ce power down current?cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , we , bhe , and ble ) v cc(max) =2.25v 1 7 a i sb2 [7] automatic ce power down current?cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0 v cc(max) =2.25v 1 7 a capacitance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 4. v il(min) = ?2.0v for pulse durations less than 20 ns. 5. v ih(max) =v cc +0.5v for pulse durations less than 20 ns. 6. full device ac operation assumes a minimum of 100 s ramp time from 0 to v cc(min) and 200 s wait time after v cc stabilization. 7. only chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating.
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 4 of 12 thermal resistance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions vfbga package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 c/w jc thermal resistance (junction to case) 10 c/w ac test loads and waveforms figure 2. ac test loads and waveforms parameters 1.80v unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v data retention characteristics over the operating range parameter description conditions min typ [1] max unit v dr v cc for data retention 1.0 v i ccdr [7] data retention current v cc = 1.0v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 0.5 5 a t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns data retention waveform figure 3. data retention waveform [10] v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent v cc(min) v cc(min) t cdr v dr > 1.0v data retention mode t r v cc ce or bhe .ble notes 8. tested initially and after any design or proce ss changes that may affect these parameters. 9. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 10. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling ch ip enable signals or by disabling both bhe and ble .
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 5 of 12 switching characteristics over the operating range [11, 12] parameter description 55 ns unit min max read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha data hold from address change 10 ns t ace ce low to data valid 55 ns t doe oe low to data valid 25 ns t lzoe oe low to low z [13] 5ns t hzoe oe high to high z [13, 14] 18 ns t lzce ce low to low z [13] 10 ns t hzce ce high to high z [13, 14] 18 ns t pu ce low to power up 0ns t pd ce high to power down 55 ns t dbe ble /bhe low to data valid 55 ns t lzbe ble /bhe low to low z [13] 10 ns t hzbe ble /bhe high to high z [13, 14] 18 ns write cycle [15] t wc write cycle time 45 ns t sce ce low to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble /bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high z [13, 14] 18 ns t lzwe we high to low z [13] 10 ns notes 11. test conditions for all parameters other than tri-state para meters assume signal transition time of 1v/ns or less, timing re ference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 4 section. 12. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 13. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the output enters a high impedence state 15. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write.
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 6 of 12 switching waveforms figure 4 shows the read cycle no.1 that is address transition controlled. [16, 17] figure 4. read cycle no. 1 figure 5 shows the read cycle no.2 that is oe controlled . [17, 18] figure 5. read cycle no. 2 previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes: 16. the device is continuously selected. oe , ce = v il , bhe , ble or both = v il . 17. we is high for read cycle. 18. address valid before or similar to ce and bhe , ble transition low.
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 7 of 12 figure 6 shows the write cycle no.1 that is we controlled. [15, 19, 20] figure 6. write cycle no. 1 figure 7 shows the write cycle no.2 that is ce controlled. [15, 19, 20] figure 7. write cycle no. 2 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 21 t bw t sce data io address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data io oe bhe /ble note 21 notes: 19. data io is high impedance if oe = v ih . 20. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 21. during this period, the ios are in output state. do not apply input signals.
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 8 of 12 figure 8 shows the write cycle no. 3 that is we controlled and oe low. [20] figure 8. write cycle no. 3 figure 9 shows write cycle no. 4 that is bhe /ble controlled and oe low. [20] figure 9. write cycle no. 4 switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 21 ce address we data io bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 21 data io address ce we bhe /ble
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 9 of 12 truth table ce we oe bhe ble inputs or outputs mode power hxxxxhigh z deselect or power down sta ndby (i sb ) l x x h h high z deselect or power down standby (i sb ) l h l l l data out (io 0 ?io 15 ) read active (i cc ) lhlhldata out (io 0 ?io 7 ); io 8 ?io 15 in high-z read active (i cc ) l h l l h data out (io 8 ?io 15 ); io 0 ?io 7 in high-z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (io 0 ?io 15 ) write active (i cc ) l l x h l data in (io 0 ?io 7 ); io 8 ?io 15 in high-z write active (i cc ) l l x l h data in (io 8 ?io 15 ); io 0 ?io 7 in high-z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 55 CY62147EV18LL-55BVXI 51-85150 48-ball vfbga (pb-free) industrial contact your local cypress sales representative for availability of other parts.
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 10 of 12 package diagram figure 10. 48-ball vfbga (6 x 8 x 1 mm), 51- 85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d
cy62147ev18 mobl2? document #: 38-05441 rev. *f page 11 of 12 document history page document title: cy62147ev18 mobl2? 4-mbit (256k x 16) static ram document number: 38-05441 rev. ecn no. issue date orig. of change description of change ** 201580 01/08/04 aju new datasheet *a 247009 see ecn syt changed from advance information to preliminary moved product portfolio to page 2 changed v ccmax from 2.20 to 2.25 v changed v cc stabilization time in footnote #8 from 100 s to 200 s removed footnote #15 (t lzbe ) from previous revision changed i ccdr from 2.0 a to 2.5 a changed typo in data retention characteristics (t r ) from 100 s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzbe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce and t bw from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to 18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin changed ordering information to include pb-free packages *b 414820 see ecn zsd changed from preliminary to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35 ns speed bin removed ?l? version of cy62147ev18 changed ball e3 from dnu to nc changed i cc (typ) value from 1.5 ma to 2 ma at f = 1 mhz changed i cc (max) value from 2 ma to 2.5 ma at f = 1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max changed i sb1 and i sb2 typ values from 0.7 a to 1 a and max values from 2.5 a to 7 a extended undershoot limit to ?2v in footnote #5 changed i ccdr max from 2.5 a to 3 a added i ccdr typical value changed t lzoe from 3 ns to 5 ns changed t lzce , t lzbe and t lzwe from 6 ns to 10 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns changed t sd from 22 ns to 25 ns updated the package diagram 48-pin vfbga from *b to *d updated the ordering information table and replaced package name column with package diagram *c 571786 see ecn vkn replaced 45ns speed bin with 55 ns *d 908120 see ecn vkn added footnote #8 related to i sb2 and i ccdr added footnote #13 related ac timing parameters changed t wc specification from 45 ns to 55 ns changed t sce , t aw , t pwe , t bw spec from 35 ns to 40 ns changed t hzwe specification from 18 ns to 20 ns
cy62147ev18 mobl2? ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document #: 38-05441 rev. *f revis ed august 01, 2007 page 12 of 12 mobl is a registered trademark, and more battery life is a trademark of cypress semiconductor. all product and company names me ntioned in this document are the trademarks of their respective holders . *e 1045701 see ecn vkn changed i ccdr specification from 3 a to 5 a *f 1274728 see ecn vkn/aesa changed t wc specification from 55 ns to 45 ns changed t sce , t aw , t pwe , t bw specification from 40 ns to 35 ns changed t hzwe specification from 20 ns to 18 ns document title: cy62147ev18 mobl2? 4-mbit (256k x 16) static ram document number: 38-05441 rev. ecn no. issue date orig. of change description of change

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